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Freescale Semiconductor Technical Data
Document Number: MC13202 Rev. 1.4, 07/2008
MC13202
MC13202
2.4 GHz Low Power Transceiver for the IEEE(R) 802.15.4 Standard
Device
Package Information Plastic Package Case 1311-03 Ordering Information Device Marking 13202 13202 Package QFN-32 QFN-32
MC13202FC MC13202FCR2 (Tape and Reel)
1
Introduction
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4 Data Transfer Modes . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . 12 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 15 Crystal Oscillator Reference Frequency . . 19 Transceiver RF Configurations and External Connections 22 10Packaging Information . . . . . . . . . . . . . . . . 29 1 2 3 4 5 6 7 8 9
The MC13202 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13202 contains a complete 802.15.4 physical layer (PHY) modem designed for the IEEE(R) 802.15.4 Standard which supports peer-to-peer, star, and mesh networking. The MC13202 includes the 802.15.4 PHY/MAC for use with the HCS08 Family of MCUs. The MC13202 can be used with Freescale's IEEE 802.15.4 MAC and BeeStack, which is Freescale's ZigBee 2006 compliant protocol stack. When combined with an appropriate microcontroller (MCU), the MC13202 provides a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBeeTM networking. For
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2005, 2006, 2007, 2008. All rights reserved.
more detailed information about MC13202 operation, refer to the MC13202 Reference Manual, (MC13202RM). Applications include, but are not limited to, the following: * Residential and commercial automation -- Lighting control -- Security -- Access control -- Heating, ventilation, air-conditioning (HVAC) -- Automated meter reading (AMR) * Industrial Control -- Asset tracking and monitoring -- Homeland security -- Process management -- Environmental monitoring and control -- HVAC -- Automated meter reading * Health Care -- Patient monitoring -- Fitness monitoring * Consumer -- Human interface devices (keyboard, mice, etc.) -- Remote control -- Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifiers (PA), onboard RF transmit/receive (T/R) switch for single port use, PLL with internal voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing per the 802.15.4 Standard. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control.
2
* * * * *
Features
Recommended power supply range: 2.0 to 3.4 V Fully compliant 802.15.4 Standard transceiver supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode Operates on one of 16 selectable channels in the 2.4 GHz band -1 to 0 dBm nominal output power, programmable from -27 dBm to +3 dBm typical Receive sensitivity of <-92 dBm (typical) at 1% PER, 20-byte packet, much better than the 802.15.4 Standard of -85 dBm
MC13202 Technical Data, Rev. 1.4
2
Freescale Semiconductor
* * *
* * * * * * * *
Integrated transmit/receive switch Dual PA output pairs which can be programmed for full differential single port or dual port operation that supports an external LNA and/or PA Three power down modes for increased battery life -- < 1 A Off current -- 1.0 A Typical Hibernate current -- 35 A Typical Doze current (no CLKO) Programmable frequency clock output (CLKO) for use by MCU Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration Four internal timer comparators available to supplement MCU timer resources Supports both Packet Mode and Streaming Mode data transfer Buffered transmit and receive data packets for simplified use with low cost MCUs Seven GPIO to supplement MCU GPIO Operating temperature range: -40 C to 85 C Small form factor QFN-32 Package -- Meets moisture sensitivity level (MSL) 3 -- 260 C peak reflow temperature -- Meets lead-free requirements
2.1
Software Features
Freescale provides a wide range of software functionality to complement the MC13202 hardware. There are three levels of application solutions: 1. Simple proprietary wireless connectivity. 2. User networks built on the 802.15.4 MAC standard. 3. ZigBee-compliant network stack.
2.1.1
* * * *
Simple MAC (SMAC)
Small memory footprint (about 3 Kbytes typical) Supports point-to-point and star network configurations Proprietary networks Source code and application examples provided
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 3
2.1.2
* * * *
802.15.4 Standard-Compliant MAC
Supports star, mesh and cluster tree topologies Supports beaconed networks Supports GTS for low latency Multiple power saving modes (idle doze, hibernate)
2.1.3
* * *
ZigBee-Compliant Network Stack
Supports ZigBee 1.0 specification Supports star, mesh and tree networks Advanced Encryption Standard (AES) 128-bit security
3
Block Diagrams
Figure 1 shows a simplified block diagram of the MC13202 which is an 802.15.4 Standard compatible transceiver that provides the functions required in the physical layer (PHY) specification.
Symbol Synch & Det
Correlator
1st IF Mix er LNA IF = 65 MHz
2nd IF Mix er IF = 1 MHz PMA
Decimation Baseband Matched Filter Mix er Filter Packet Processor
Analog Regulator Pow er-Up Control Logic Digital Regulator L Digital Regulator H Cry stal Regulator
VDDA VBATT VDDINT VDDD
CCA
DCD
RFIN_P (PAO_P) RFIN_M (PAO_M) T/ R AGC
Receiv e Packet RAM
Receiv e RAM Arbiter Sequence Manager (Control Logic)
VCO Regulator
VDDVCO
CT_Bias VDDLO2
256 MHz
RXTXEN
/4
Programmable Prescaler
24 Bit Ev ent Timer
XTAL1 XTAL2
Crystal Oscillator
16 MHz
SERIAL PERIPHERAL INTERFACE (SPI)
4 Programmable Timer Comparators
CE MOSI MISO SPICLK ATTN RST
Synthesizer
Transmit Packet RAM 2 Transmit Packet RAM 1
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Transmit RAM Arbiter Sy mbol Generation IRQ Arbiter IRQ
VDDLO1
2.45 GHz VCO
PAO_P PAO_M
PA
Phase Shift Modulator
MUX
CLKO
FCS Generation
Header Generation
Figure 1. 802.15.4 Modem Simplified Block Diagram
MC13202 Technical Data, Rev. 1.4 4 Freescale Semiconductor
Figure 2 shows the basic system block diagram for the MC13202 in an application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control (MAC), drivers, and network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements.
MC13202 Analog Receiver Digital Transceiver Control Logic SPI and GPIO Microcontroller SPI Timer A/D ROM (Flash) RAM RAM Arbiter IRQ Arbiter Timer CPU Application Network Voltage Regulators Power Up Management Buffer RAM MAC PHY Driver
Frequency Generation
Analog Transmitter
Figure 2. System Level Block Diagram
4
Data Transfer Modes
The MC13202 has two data transfer modes: 1. Packet Mode -- Data is buffered in on-chip RAM 2. Streaming Mode -- Data is processed word-by-word The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary applications, packet mode can be used to conserve MCU resources.
4.1
Packet Structure
Figure 3 shows the packet structure of the MC13202. Payloads of up to 125 bytes are supported. The MC13202 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and appended to the end of the data.
4 bytes Preamble 1 byte SFD 1 byte FLI 125 bytes maximum Payload Data 2 bytes FCS
Figure 3. MC13202 Packet Structure
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 5
4.2
Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon the baseband energy integrated over a specific time interval. The digital backend performs Differential Chip Detection (DCD), the correlator "de-spreads" the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data. The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 s period after the packet preamble and stored in RAM. If the MC13202 is in packet mode, the data is processed as an entire packet. The MCU is notified that an entire packet has been received via an interrupt. If the MC13202 is in streaming mode, the MCU is notified by an interrupt on a word-by-word basis. Figure 4 shows CCA reported power level versus input power. Note that CCA reported power saturates at about -57 dBm input power which is well above 802.15.4 Standard requirements. Figure 5 shows energy detection/LQI reported level versus input power. NOTE For both graphs, the required 802.15.4 Standard accuracy and range limits are shown. A 3.5 dBm offset has been programmed into the CCA reporting level to center the level over temperature in the graphs.
-50
Reported Power Level (dBm)
-60
-70
802.15.4 Ac curac y and range Requirements
-80
-90
-100 -90
-80
-70 Input Pow er (dBm)
-60
-50
Figure 4. Reported Power Level versus Input Power in CCA Mode
MC13202 Technical Data, Rev. 1.4 6 Freescale Semiconductor
-15 -25 Reported Power Level (dBm) -35 -45 -55 -65 -75 -85 -85 -75 -65 -55 -45 -35 -25 -15 Input Power Level (dBm) 802.15.4 Accuracy and Range Requirements
Figure 5. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
4.3
Transmit Path Description
For the transmit path, the TX data that was previously stored in RAM is retrieved (packet mode) or the TX data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency. If the MC13202 is in packet mode, data is processed as an entire packet. The data are first loaded into the TX buffer. The MCU then requests that the MC13202 transmit the data. The MCU is notified via an interrupt when the whole packet has successfully been transmitted. In streaming mode, the data is fed to the MC13202 on a word-by-word basis with an interrupt serving as a notification that the MC13202 is ready for more data. This continues until the whole packet is transmitted.
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 7
5
5.1
Electrical Characteristics
Maximum Ratings
Table 1. Maximum Ratings
Rating Power Supply Voltage Digital Input Voltage RF Input Power Junction Temperature Storage Temperature Range Symbol VBATT, VDDINT Vin Pmax TJ Tstg Value -0.3 to 3.6 -0.3 to (VDDINT + 0.3) 10 125 -55 to 125 dBm C C Unit Vdc
Note: Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables. Note: Meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection.
5.2
Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Characteristic Symbol VBATT, VDDINT fin TA VIL VIH fSPI Pmax fref Min 2.0 2.405 -40 0 70% VDDINT Typ 2.7 25 Max 3.4 2.480 85 30% VDDINT VDDINT 8.0 10 Unit Vdc GHz C V V MHz dBm
Power Supply Voltage (VBATT = VDDINT)1 Input Frequency Ambient Temperature Range Logic Input Voltage Low Logic Input Voltage High SPI Clock Rate RF Input Power Crystal Reference Oscillator Frequency (40 ppm over operating conditions to meet the 802.15.4 Standard.)
1
16 MHz Only
If the supply voltage is produced by a switching DC-DC converter, ripple should be less than 100 mV peak-to-peak.
MC13202 Technical Data, Rev. 1.4 8 Freescale Semiconductor
5.3
DC Electrical Characteristics
Table 3. DC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit
Power Supply Current (VBATT + VDDINT) Off1 Hibernate1 Doze (No CLKO)1 2 Idle Transmit Mode (0 dBm nominal output power) Receive Mode Input Current (VIN = 0 V or VDDINT) (All digital inputs) Input Low Voltage (All digital inputs) Input High Voltage (all digital inputs) Output High Voltage (IOH = -1 mA) (All digital outputs) Output Low Voltage (IOL = 1 mA) (All digital outputs)
1
Ileakage ICCH ICCD ICCI ICCT ICCR IIN VIL VIH VOH VOL
0 70% VDDINT 80% VDDINT 0
0.2 1.0 35 500 30 37 -
1.0 6.0 102 800 35 42 1 30% VDDINT VDDINT VDDINT 20% VDDINT
A A A A mA mA A V V V V
To attain specified low power current, all GPIO and other digital IO must be handled properly. See Section 8.3, "Low Power Considerations". 2 CLKO frequency at default value of 32.786 kHz.
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 9
5.4
AC Electrical Characteristics
Table 4. Receiver AC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 C, fref = 16 MHz, unless otherwise noted.) Characteristic Symbol SENSper Min SENSmax Typ -92 -92 10 31 30 43 41 53 Max -87 200 80 Unit dBm dBm dBm dB dB dB dB dB kHz ppm
Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 C) Sensitivity for 1% Packet Error Rate (PER) (+25 C) Saturation (maximum input level) Channel Rejection for 1% PER (desired signal -82 dBm) +5 MHz (adjacent channel) -5 MHz (adjacent channel) +10 MHz (alternate channel) -10 MHz (alternate channel) >= 15 MHz Frequency Error Tolerance Symbol Rate Error Tolerance
Table 5. Transmitter AC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 C, fref = 16 MHz, unless otherwise noted.) Characteristic Power Spectral Density (-40 to +85 C) Absolute limit Power Spectral Density (-40 to +85 C) Relative limit Nominal Output Power
1
Symbol
Min -
Typ -47 47 -1 4
Max 2
Unit dBm
Pout
-4
dBm dBm
Maximum Output Power2 Error Vector Magnitude Output Power Control Range Over the Air Data Rate 2nd Harmonic3 3rd Harmonic
1 2 3
EVM
-
20 30 250 -48 -70
35 -
% dB kbps dBc dBc
SPI Register 12 programmed to 0x00BC which sets output power to nominal (-1 dBm typical). SPI Register 12 programmed to 0x00FF which sets output power to maximum. 3 Measured with output power set to nominal (0 dBm) and temperature @ 25 C
MC13202 Technical Data, Rev. 1.4 10 Freescale Semiconductor
Table 6. Digital Timing Specifications (VBATT, VDDINT = 2.7 V, TA = 25 C, frequency = 16 MHz, unless otherwise noted.
SPI timing parameters are referenced to Figure 8. Symbol T0 T1 T2 T3 T4 T5 T6 T7 SPICLK period Pulse width, SPICLK low Pulse width, SPICLK high Delay time, MISO data valid from falling SPICLK Setup time, CE low to rising SPICLK Delay time, MISO valid from CE low Setup time, MOSI valid to rising SPICLK Hold time, MOSI valid from rising SPICLK RST minimum pulse width low (asserted) 250 Parameter Min 125 50 50 15 15 15 15 15 Typ Max Unit nS nS nS nS nS nS nS nS nS
Figure 6 shows a typical AC parameter evaluation circuit.
U5 L1 PAO_M PAO_P RFIN_P RFIN_M CT_Bias MC1320x 6 5 2 1 3 L4 1.8nH 1.8nH 3 L2 6.8nH 2 4 Z1 1 5 6 LDB212G4005C-001 L3 3.9nH C1 1.0pF R2 0R Not Mounted ANT1 F_Antenna R1 0R
C2 10pF 2 3 4 5 1 J1 SMA_edge_Receptac
Figure 6. RF Parametric Evaluation Circuit
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 11
6
Functional Description
The following sections provide a detailed description of the MC13202 functionality including the operating modes and Serial Peripheral Interface (SPI).
6.1
MC13202 Operational Modes
The MC13202 has a number of operational modes that allow for low-current operation. Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table 7. Current drain in the various modes is listed in Table 3, DC Electrical Characteristics.
Table 7. MC13202 Mode Definitions and Transition Times
Mode Off Hibernate Doze Definition All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including IRQ Transition Time To or From Idle 10 - 25 ms to Idle
Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is 7 - 20 ms to Idle retained. Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = (300 + 1/CLKO) s to Idle 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator. Crystal Reference Oscillator On with CLKO output available. SPI active. Crystal Reference Oscillator On. Receiver On. Crystal Reference Oscillator On. Transmitter On. 144 s from Idle 144 s from Idle
Idle Receive Transmit
6.2
Serial Peripheral Interface (SPI)
The host microcontroller directs the MC13202, checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and the MC13202 occurs as multiple 8-bit bursts on the SPI. The SPI signals are: 1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts. 2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13202. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK. NOTE For Freescale microcontrollers, the SPI clock format is the clock phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0. 3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input. 4. Master In/Slave Out (MISO) - The MC13202 presents data to the master on the MISO output.
MC13202 Technical Data, Rev. 1.4 12 Freescale Semiconductor
A typical interconnection to a microcontroller is shown in Figure 7.
MCU MC13202
Shift Register
RxD TxD Sclk
MISO MOSI SPICLK Shift Register
Baud Rate Generator
Chip Enable (CE)
CE
Figure 7. SPI Interface
Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock (CLKcore), derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory.
6.2.1
SPI Burst Operation
The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13202 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure 8.
SPI Burst
CE 1 SPIC L K T4 T6 T5 T7 M ISO M O SI V alid V alid T3 V alid T2 T1 T0 2 3 4 5 6 7 8
Figure 8. SPI Single Burst Timing Diagram
SPI digital timing specifications are shown in Table 6.
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 13
6.2.2
SPI Transaction Operation
Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13202 requires that a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. In this context, a write is data written to the MC13202 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13202 never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. The number of payload bytes sent will always be an even integer. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the MC13202 Reference Manual, (MC13202RM) for more details on SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure 9.
CE C lo c k B u rst S P IC L K
M IS O
V a lid
V a lid
M O SI
V a lid H eader R e a d d a ta
Figure 9. SPI Read Transaction Diagram
MC13202 Technical Data, Rev. 1.4 14 Freescale Semiconductor
7
Pin # 1
Pin Connections
Table 8. Pin Function Description
Pin Name RFIN_M Type RF Input Description RF input/output negative. Functionality When used with internal T/R switch, this is a bi-directional RF port for the internal LNA and PA When used with internal T/R switch, this is a bi-directional RF port for the internal LNA and PA
2
RFIN_P
RF Input
RF input/output positive.
3
CT_Bias
Control voltage
Bias voltage/control signal for external When used with internal T/R switch, RF components provides RX ground reference and TX VDDA reference for use with external balun. Can also be used as a control signal for external LNA, PA, or T/R switch. Tie to Ground.
4 5
NC PAO_P
RF Output /DC Input RF Power Amplifier Output Positive.
Open drain. Connect to VDDA through a bias network when used with an external balun. Not used when internal T/R switch is used.
6
PAO_M
RF Output/DC Input RF Power Amplifier Output Negative. Open drain. Connect to VDDA through a bias network when used with an external balun. Not used when internal T/R switch is used. Input Test mode pin. Must be grounded for normal operation. See Footnote 1 See Footnote 1
7 8 9 10
SM GPIO41 GPIO31 GPIO21
Digital Input/ Output General Purpose Input/Output 4. Digital Input/ Output General Purpose Input/Output 3.
Digital Input/ Output General Purpose Input/Output 2. See Footnote 1 When gpio_alt_en, Register 9, Bit 7 = 1, GPIO2 functions as a "CRC Valid" indicator. Digital Input/ Output General Purpose Input/Output 1. See Footnote 1 When gpio_alt_en, Register 9, Bit 7 = 1, GPIO1 functions as an "Out of Idle" indicator. Digital Input Active Low Reset. While held low, the IC is in Off Mode and all internal information is lost from RAM and SPI registers. When high, IC goes to IDLE Mode, with SPI in default state.
11
GPIO11
12
RST
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 15
Table 8. Pin Function Description (continued)
Pin # 13 Pin Name RXTXEN2 Type Digital Input Description Active High. Low to high transition initiates RX or TX sequence depending on SPI setting. Should be taken high after SPI programming to start RX or TX sequence and should be held high through the sequence. After sequence is complete, return RXTXEN to low. When held low, forces Idle Mode. Functionality See Footnote 2
14
ATTN2
Digital Input
Active Low Attention. Transitions IC See Footnote 2 from either Hibernate or Doze Modes to Idle. Clock output to host MCU. Programmable frequencies of: 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz, 32.786+ kHz (default), and 16.393+ kHz. External clock input for the SPI interface. Master Out/Slave In. Dedicated SPI data input. Master In/Slave Out. Dedicated SPI data output. See Footnote 2 See Footnote 2 See Footnote 3
15
CLKO
Digital Output
16 17 18 19 20
SPICLK2 MOSI2 MISO3 CE2 IRQ
Digital Clock Input Digital Input Digital Output Digital Input Digital Output
Active Low Chip Enable. Enables SPI See Footnote 2 transfers. Active Low Interrupt Request. Open drain device. Programmable 40 k internal pull-up. Interrupt can be serviced every 6 s with <20 pF load. Optional external pull-up must be >4 k. Decouple to ground. 2.0 to 3.4 V. Decouple to ground. See Footnote 1 See Footnote 1 See Footnote 1 Connect to 16 MHz crystal and load capacitor.
21 22 23 24 25 26
VDDD VDDINT GPIO51 GPIO61 GPIO71 XTAL1
Power Output Power Input Digital Input/Output Digital Input/Output Digital Input/Output Input
Digital regulated supply bypass. Digital interface supply & digital regulator input. Connect to Battery. General Purpose Input/Output 5. General Purpose Input/Output 6. General Purpose Input/Output 7. Crystal Reference oscillator input.
MC13202 Technical Data, Rev. 1.4 16 Freescale Semiconductor
Table 8. Pin Function Description (continued)
Pin # 27 Pin Name XTAL2 Type Input/Output Description Crystal Reference oscillator output Note: Do not load this pin by using it as a 16 MHz source. Measure 16 MHz output at Pin 15, CLKO, programmed for 16 MHz. See the MC13202 Reference Manual for details. LO2 VDD supply. Connect to VDDA externally. LO1 VDD supply. Connect to VDDA externally. VCO regulated supply bypass. Analog voltage regulators Input. Connect to Battery. Analog regulated supply Output. Connect to directly VDDLO1 and VDDLO2 externally and to PAO through a bias network. Note: Do not use this pin to supply circuitry external to the chip. External paddle / flag ground. Decouple to ground. Decouple to ground. Decouple to ground. Functionality Connect to 16 MHz crystal and load capacitor.
28 29 30 31 32
VDDLO2 VDDLO1 VDDVCO VBATT VDDA
Power Input Power Input Power Output Power Input Power Output
EP
1
Ground
Connect to ground.
The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state. 2 During low power modes, input must remain driven by MCU. 3 By default MISO is tri-stated when CE is negated. For low power operation, miso_hiz_en (Bit 11, Register 07) should be set to zero so that MISO is driven low when CE is negated.
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 17
32 VDDA
31 VBATT
30 VDDVCO
29 VDDLO1
28 VDDLO2
27 XTAL2
26 XTAL1
25 GPIO7
1 2 3 4 5 6 7 8
RFIN_M RFIN_P CT_Bias NC
GPIO6 GPIO5
24 23 22 21 20 19 18 17
VDDINT VDDD EP
PAO_P PAO_M SM
MC13202
RXTXEN GPIO2 GPIO1 SPICLK 16 CLKO
IRQ CE MISO
GPIO3
GPIO4
MOSI
9
10
11
12
RST
13
14
ATTN
15
Figure 10. Pin Connections (Top View)
MC13202 Technical Data, Rev. 1.4 18 Freescale Semiconductor
8
Crystal Oscillator Reference Frequency
This section provides application specific information regarding crystal oscillator reference design and recommended crystal usage.
8.1
Crystal Oscillator Design Considerations
The 802.15.4 Standard requires that several frequency tolerances be kept within 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13202 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal resonant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal resonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - initial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. 5. Whether or not a frequency trim step will be performed in production Freescale requires the use of a 16 MHz crystal with a <9 pF load capacitance. The MC13202 does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13202 requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading. In the Figure 11 crystal reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps.
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 19
U6 XTAL1 26 Y1 16MHz XTAL2 MC1320x 27 C10 6.8pF
C11 6.8pF
Y1 = Daishinku KDS - DSX321G ZD00882
Figure 11. MC13202 Modem Crystal Circuit
Initial tolerance for the internal trim capacitance is approximately 15%. Since the MC13202 contains an on-chip reference frequency trim capability, it is possible to trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a board-by-board basis. Individual trimming of each board in a production environment allows use of the lowest cost crystal, but requires that each board go through a trimming procedure. This step can be avoided by using/specifying a crystal with a tighter stability tolerance, but the crystal will be slightly higher in cost. A tolerance analysis budget may be created using all the previously stated factors. It is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging factor is usually specified in ppm/year and the product designer can determine how many years are to be assumed for the product lifetime. Taking all of the factors into account, the product designer can determine the needed specifications for the crystal and external load capacitors to meet the 802.15.4 Standard.
8.2
Crystal Requirements
The suggested crystal specification for the MC13202 is shown in Table 9. A number of the stated parameters are related to desired package, desired temperature range and use of crystal capacitive load trimming. For more design details and suggested crystals, see application note AN3251, Reference Oscillator Crystal Requirements for MC1319x, MC1320x, and MC1321x.
Table 9. MC13202 Crystal Specifications1
Parameter Frequency Frequency tolerance (cut tolerance)2 Value 16.000000 10 15 2 43 5-9 <2 Unit MHz ppm ppm ppm pF pF max fundamental at 25 C Over desired temperature range max max Condition
Frequency stability (temperature drift)3 Aging
4
Equivalent series resistance5 Load capacitance
6
Shunt capacitance Mode of oscillation
1 2
User must be sure manufacturer specifications apply to the desired package. A wider frequency tolerance may acceptable if application uses trimming at production final test.
MC13202 Technical Data, Rev. 1.4 20 Freescale Semiconductor
3 4
A wider frequency stability may be acceptable if application uses trimming at production final test. A wider aging tolerance may be acceptable if application uses trimming at production final test. 5 Higher ESR may be acceptable with lower load capacitance. 6 Lower load capacitance can allow higher ESR and is better for low temperature operation in Doze mode.
8.3
*
Low Power Considerations
Program and use the modem IO pins properly for low power operation -- All unused modem GPIOx signals must be used one of 2 ways: - If the Off mode is to be used as a long term low power mode, unused GPIO should be tied to ground. The default GPIO mode is an input and there will be no conflict. - If only Hibernate and/or Doze modes are used as long term low power modes, the GPIO should programmed as outputs in the low state. -- When modem GPIO are used as outputs: - Pullup resistors should be provided (can be provided by the MCU IO pin if tied to the MCU) if the modem Off condition is to be used as a long term low power mode. - During Hibernate and/or Doze modes, the GPIO will retain its programmed output state. -- If the modem GPIO is used as an input, the GPIO should be driven by its source during all low power modes or a pullup resistor should be provided. -- Digital outputs IRQ, MISO, and CLKO: - MISO - is always an output. During Hibernate, Doze, and active modes, the default condition is for the MISO output to go to tristate when CE is de-asserted, and this can cause a problem with the MCU because one of its inputs can float. Program Control_B Register 07, Bit 11, miso_hiz_en = 0 so that MISO is driven low when CE is de-asserted. As a result, MISO will not float when Doze or Hibernate Mode is enabled. - IRQ - is an open drain output (OD) and should always have a pullup resistor (typically provided by the MCU IO). IRQ acts as the interrupt request output. NOTE It is good practice to have the IRQ interrupt input to the MCU disabled during the hardware reset to the modem. After releasing the modem hardware reset, the interrupt request input to the MCU can then be enabled to await the IRQ that signifies the modem is ready and in Idle mode; this can prevent a possible extraneous false interrupt request. - CLKO - is always an output. During Hibernate CLKO retains its output state, but does not toggle. During Doze, CLKO may toggle depending on whether it is being used. If the MCU is also going to be used in low power modes, be sure that all unused IO are programmed properly for low power operation (typically best case is as outputs in the low state). The MC13202 is commonly used with the Freescale MC9S08GT/GB 8-bit devices. For these MCUs: -- Use only STOP2 and STOP3 modes (not STOP1) with these devices where the GPIO states are retained. The MCU must retain control of the MC13202 IO during low power operation. -- As stated above all unused GPIO should be programmed as outputs low for lowest power and no floating inputs.
MC13202 Technical Data, Rev. 1.4
*
Freescale Semiconductor
21
-- MC9S08GT devices have IO signals that are not pinned-out on the package. These signals must also be initialized (even though they cannot be used) to prevent floating inputs.
9
Transceiver RF Configurations and External Connections
The MC13202 radio has features that allow for a flexible as well as low cost RF interface: * Programmable output power -- 0 dBm nominal output power, programmable from -27 dBm to +4 dBm typical * <-94 dBm (typical) receive sensitivity -- At 1% PER, 20-byte packet (well above 802.15.4 Standard of -85 dBm) * Optional integrated transmit/receive (T/R) switch for low cost operation -- With internal PAs and LNA, the internal T/R switch allows a minimal part count radio interface using only a single balun to interface to a single-ended antenna * Maximum flexibility -- There are full differential RF I/O pins for use with the internal T/R switch. Optionally, these pins become the RF_IN signals and a separate set of full differential PA outputs are also provided. Separate inputs and outputs allow for a variety of RF configurations including external LNA and PA for increased range * CT_Bias Output -- The CT_Bias signal provides a switched bias reference for use with the internal T/R switch, and alternatively can be programmed as an antenna switch signal for use with an external antenna switch * Onboard trim capability for 16 MHz crystal reference oscillator -- The 802.15.4 Standard puts a +/- 40 ppm requirement on the carrier frequency. The onboard trim capability of the modem crystal oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration. Also tighter tolerance can produce greater receive sensitivity
9.1
RF Interface Pins
Figure 12 shows the RF interface pins and the associated analog blocks. Notice that separate PA blocks are associated with RFIN_x and PAO_x signal pairs. The RF interface allows both single port differential operation and dual port differential operation.
MC13202 Technical Data, Rev. 1.4 22 Freescale Semiconductor
2 1
RFIN_P (PAO_P) RFIN_M (PAO_M) RX SW ITCH LNA RX SIGNAL
RX ENABLE PA2 3 CT_Bias PA2 ENABLE CT_Bias Generator 5 6 CT_Bias CONTROL PAO_P PAO_M PA1 FROM TX PSM PA1 ENABLE
Figure 12. RF Interface Pins
9.1.1
Single Port Operation
The integrated RF switch allows users to operate in a single port configuration. In Single Port Mode, an internal RX switch and separate PA are used and pins RFIN_P (PAO_P) and RFIN_M (PAO_M) become bidirectional and connect both for TX and RX. When receiving, the RX switch is enabled to the internal LNA and the TX PA is disabled. When transmitting, the RX switch is disabled (isolating the LNA) and a TX PA is enabled. The optional CT_Bias pin provides a reference or bias voltage which is at VDDA for transmit and is at ground for receive. This signal can be used to provide the proper bias voltage to a balun that converts a single-ended antenna to the differential interface required by the transceiver. Figure 13 shows a single port example with a balun.
MC13202/03
RFIN_P (PAO_P) Balun L1 RFIN_M (PAO_M) CT_Bias Bypass PAO_P
PAO_M
Figure 13. Single Port RF Operation with a Balun
The CT_Bias is connected to the balun center-tap providing the proper DC bias voltage to the balun depending on RX or TX.
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 23
9.1.2
Dual Port Operation
A second set of pins designated PAO_P and PAO_N allow operation in a dual port configuration. There are separate paths for transmit and receive with the optional CT_Bias pin providing a signal that indicates if the radio is in TX or RX Mode which then can be used to drive an external low noise amplifier, power amplifier, or antenna switch. In dual port operation, the RFIN_P and RFIN_N are inputs only, the internal RX switch to the LNA is enabled to receive, and the associated TX PA stays disabled. Pins PAO_P and PAO_N become the differential output pins and the associated TX PA is enabled for transmit. Figure 14 shows two dual port configurations. First is a single antenna configuration with an external low noise amplifier (LNA) for greater range. An external antenna switch is used to multiplex the antenna between receive and transmit. An LNA is in the receive path to add gain for greater receive sensitivity. Two external baluns are required to convert the single-ended antenna switch signals to the differential signals required by the radio. Separate RFIN and PAO signals are provided for connection with the baluns, and the CT_bias signal is programmed to provide the external switch control. The polarity of the external switch control is selectable. Figure 14 also shows a dual antenna configuration where there is a RX antenna and a TX antenna. For the receive side, the RX antenna is ac-coupled to the differential RFIN inputs and these capacitors along with inductor L1 form a matching network. Inductors L2 and L3 are ac-coupled to ground to form a frequency trap. For the transmit side, the TX antenna is connected to the differential PAO outputs, and inductors L4 and L5 provide DC-biasing to VDDA but are ac-isolated. CT_Bias is not required or used.
MC13202 Technical Data, Rev. 1.4 24 Freescale Semiconductor
VDD
A nt Sw
LN A B a lun L1
R F IN _ P (P A O _P )
R F IN _ M (P A O _ M ) B yp ass
M C 1320 2/03
C T _ B ias (A nt S w C tl) PAO_P
VDDA B a lun
PAO_M B yp ass
Using External Antenna Switch with LNA
RX Antenna
L2
L3
L1
RFIN_P (PAO_P)
RFIN_M (PAO_M)
TX Antenna Bypass VDDA Bypass
MC13202/03
L4
L5
CT_Bias
PAO_P
PAO_M
Using Dual Antenna
Figure 14. Dual Port RF Configuration Examples
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 25
9.2
Controlling RF Modes of Operation
Use of the RF interface pins and RF modes of operation are controlled through several bits of modem Control_B Register 07. Figure 15 shows the model for Register 07 with the RF interface control bits highlighted.
Register 07
BIT 15 14 ct_bias_en 13 ct_bias_inv 12 RF_switch_mode 11 miso_hiz_en 10 9 clko_doze_en 8 7 tx_done_mask 6 rx_done_mask 5 use_strm_mode 4
0x07 3 2 1 0
tmr_load
TYPE RESET
r/w r/w r/w r/w r/w 0 0 0 0 1 1
r/w 0 0
r/w r/w r/w 0 0 0 0 0 0
r/w 0
r/w 0
0x0C00
Figure 15. Control_B Register 07 Model
The RF interface control bits include: * RF_switch_mode (Bit 12) -- This bit selects Dual Port Mode versus Single Port Mode: -- The default condition (Bit 12 = 0) is Dual Port Mode where the RF inputs are RFIN_M and RFIN_P and the RF outputs are PAO_M and PAO_P, and operation is as described in Section 9.1.2, "Dual Port Operation". The use of CT_Bias pin in Dual Port Mode is controlled by Bit 13 and Bit 12. -- When Bit = 1, the Single Port Mode is selected where RFIN_M (PAO_M) and RFIN_P (PAO_P) become bidirectional pins and operation is as described in Section 9.1.1, "Single Port Operation". The use of CT_Bias pin in Dual Port Mode in controlled by Bit 13 and Bit 12. * Ct_bias_en (Bit 14) -- This bit is the enable for the CT_Bias output. When Bit 14 = 0 (default), the CT_Bias is disabled and stays in a Hi-Z or tri-stated condition. When Bit 14 = 1, the CT_Bias output is active and its state is controlled by the selected mode (Bit 12), ct_bias_inv, and operation of the radio. * Ct_bias_inv (Bit 13) -- This bit only affects the state of CT_Bias when Dual Port Mode is selected and CT_bias is active. The CT_Bias changes state in Dual Port Mode based on the TX or RX state of the radio. The ct_bias_inv bit causes the sense of the active state to change or invert based on Bit 13's setting. In this manner, the user can select the CT_Bias as a control signal for external components and make the control signal active high or active low.
MC13202 Technical Data, Rev. 1.4 26 Freescale Semiconductor
doze_en
hib_en
Table 10 summarizes the operation of the RF interface control bits.
Table 10. RF Interface Control Bits
Bit 14 13 Designation ct_bias_en ct_bias_inv Default 0 0 Operation 1 = CT_Bias enabled. Output state is defined by Table 11. 0 = CT_Bias disabled. Output state is tri-stated. The output state of CT_Bias under varying conditions is defined in Table 11. This bit only has effect for dual port operation. 1 = CT_Bias inverted. 0 = CT_Bias not inverted 1= Single Port Mode selected where RF switch is active and RFIN_M and RFIN_P and bidirectional signals. 0 = Dual Port Mode selected where RFIN_M and RFIN_P are inputs only and PAO_P and PAO_N are separate outputs. (This is default operation).
12
RF_switch_mode
0
9.3
RF Control Output CT_Bias
CT_Bias is a useful signal for interface with external RF components. It must be enabled via the ct_bias_en control bit, and then its state is determined first by the selected RF mode and then by the active state of the radio, i.e., whether a TX or RX operation is active: * Single Port Operation -- In this mode, the CT_Bias can be used to establish the proper DC bias voltage to a balun depending on the RX state versus TX state as described in Section 9.1.1, "Single Port Operation". Note that in single port operation, the ct_bias_inv has no effect and CT_Bias is at VDDA for TX and is at ground for RX * Dual Port Operation -- In this mode, the CT_Bias can be used as a control signal to enable a LNA or PA or to determine the direction of an antenna switch as described in Section 9.1.2, "Dual Port Operation". In dual port operation, ct-bias_inv is used to control the sense of the output control, i.e., CT_Bias can be active high or active low for TX and vice-versa for RX Table 11 defines the CT_Bias output state depending on control bits and operation mode of the modem. Note that the output state is also defined in Idle, Hibernate, and Doze state as well as RX and TX operation.
Table 11. CT_Bias Output vs. Register Settings
Mode RX RX RX RX RX TX TX TX CT_Bias_en 1 1 1 0 1 1 1 1 RF_switch_mode 1 1 0 X 1 1 1 0 CT_Bias_inv 0 1 0 X 0 0 1 0 0 0 0 Hi-Z 1 1 1 1 CT_Bias
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 27
Table 11. CT_Bias Output vs. Register Settings (continued)
Mode TX TX Idle Idle Doze Doze Hibernate Hibernate Off CT_Bias_en 1 0 1 0 1 0 1 0 X RF_switch_mode 0 X X X X X X X X CT_Bias_inv 1 X X X X X X X X 0 Hi-Z 0 Hi-Z 0 Hi-Z 0 (Low-Z) Hi-Z Unknown CT_Bias
9.4
RF Single Port Application with an F Antenna
Figure 16 shows a typical single port RF application in which part count is minimized and a printed copper F antenna is used for low cost. Only the RFIN port of the MC13202 is required because the differential port is bi-directional and uses the on-chip T/R switch. Matching to near 50 Ohms is accomplished with L1, L2, L3, and the traces on the PCB. A balun transforms the differential signal to single-ended to interface with the F antenna. The proper DC bias to the RFIN_x (PAO_x) pins is provided through the balun. The CT_Bias pin provides the proper bias voltage point to the balun depending on operation, that is, CT_Bias is at VDDA voltage for transmit and is at ground for receive. CT_Bias is switched between these two voltages based on the operation. Capacitor C2 provides some high frequency bypass to the DC bias point. The L3/C1 network provides a simple bandpass filter to limit out-of-band harmonics from the transmitter.
U5 L1 PAO_M PAO_P RFIN_P RFIN_M CT_Bias MC1320x 6 5 2 1 3 L4 1.8nH 1.8nH 3 L2 6.8nH 2 4 Z1 1 5 6 LDB212G4005C-001 L3 3.9nH C1 1.0pF R2 0R Not Mounted ANT1 F_Antenna R1 0R
C2 10pF 2 3 4 5 1 J1 SMA_edge_Receptac
Figure 16. RF Single Port Application with an F-Antenna
MC13202 Technical Data, Rev. 1.4 28 Freescale Semiconductor
10 Packaging Information
PIN 1 INDEX AREA 0.1 A 0.1 2X C G 1.0 0.8 5 (0.25) 0.05 0.00 (0.5) C DETAIL G VIEW ROTATED 90 CLOCKWISE M B 0.1 C 3.25 2.95 EXPOSED DIE ATTACH PAD 25 24 32 A B DETAIL M PIN 1 INDEX SEATING PLANE 1.00 0.75 0.05 C 5 5 2X M 0.1 C C
1 0.25
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. COPLANARITY APPLIES TO LEADS, CORNER LEADS, AND DIE ATTACH PAD. 6. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12.
3.25 2.95 0.1 C A B 0.5 N 32X 0.30 0.18 0.1 VIEW M-M 0.05 M M C C DETAIL S PREFERRED BACKSIDE PIN 1 INDEX (45 5 ) DETAIL S A B (0.25) (0.1) 28X 0.217 0.137 17 16 32X 0.5 0.3 9 8 0.217 0.137
(1.73)
0.60 0.24
32X
0.065 0.015
(0.25) DETAIL N PREFERRED CORNER CONFIGURATION 4
0.60 0.24 DETAIL N CORNER CONFIGURATION OPTION 4 DETAIL M PREFERRED BACKSIDE PIN 1 INDEX
DETAIL T 0.475 0.425
1.6 1.5
5
BACKSIDE PIN 1 INDEX
(90 )
2X
0.39 0.31
R DETAIL M BACKSIDE PIN 1 INDEX OPTION
0.25 0.15 DETAIL M BACKSIDE PIN 1 INDEX OPTION DETAIL T BACKSIDE PIN 1 INDEX OPTION
2X
0.1 0.0
Figure 17. Outline Dimensions for QFN-32, 5x5 mm (Case 1311-03, Issue E)
MC13202 Technical Data, Rev. 1.4 Freescale Semiconductor 29
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Document Number: MC13202 Rev. 1.4 07/2008

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